1. Field of the Invention
The present invention relates to a phase locked loop system for transmitting a digital audio signal in synchronism with a video signal and then reproducing the sampling frequency of the digital audio signal.
2. Description of the Prior Art
In recording a digital audio signal by a helical scan VTR, the configuration of the VTR servo system synchronous with the vertical sync signal of the video signal generally requires the digital audio signal to have a sampling frequency of 31.968 kHz, 44.056 kHz or 47.952 kHz in synchronism with the vertical sync signal (60/1.001 Hz for NTSC system) of the video signal.
When a digital audio signal is recorded from a digital interface by the helical scan VTR in this configuration, it is necessary for the transmitting end of the digital audio signal to receive the sync clock from the VTR and transmit a digital audio signal in synchronism therewith.
Recording is, therefore, impossible from a digital audio tape recorder exclusively used for audio purposes lacking an external sync input or a digital audio unit operated with a specific sampling frequency (32 kHz, 44.1 kHz or 48 kHz, for example).
There has been proposed a digital signal processing system for synchronizing a digital audio signal of a sampling frequency Fs with a vertical sync frequency Fv of a video signal non-synchronous with the frequency Fs and recording/reproducing it together with a video signal on a helical-scan VTR (JP-A-61-233472, JP-A-62-162280, JP-A-63-29377).
This system records a digital audio signal in a plurality of sections in the number of [Fs/Fv]+A or [Fs/Fv]-B for each head-switching period. The digital audio signal thus recorded is controlled to an average output sampling rate Fs. When Fs=48 kHz, Fv=60/1.001 Hz, A=10 and B=8, for example, the digital audio signal pulses or samples numbering 810 or 792 for the head switching period are recorded by being controlled to an average of 800.8. In the head-switching period for recording 792 digital audio signal samples, 18 dummy data samples are recorded together with them to match the output rate with the output of 810 digital samples for the head-switching period. Also, when the 810 or 792 data pulses are produced in the head-switching period, a discrimination signal is recorded for discriminating the number of the digital audio signal pulses recorded during the head-switching period.
FIG. 1 shows a conventional digital signal processing system, in which numeral 501 designates a digital audio signal input terminal, numeral 502 a time-axis conversion circuit, numeral 503 an encoding circuit, numeral 504 a format control circuit, numeral 505 a modulation circuit, numeral 506 a recording amplifier, numeral 507 a pair of magnetic heads mounted on a rotary cylinder, numeral 508 a reproduction amplifier, numeral 509 a demodulation circuit, numeral 510 a reverse format control circuit, numeral 511 a decoding circuit, numeral 512 a reverse time-axis conversion circuit, numeral 513 a digital audio signal output terminal, numeral 515 a switch, and numeral 516 a switching signal generator (head switch (HSW generator).
The operation of a conventional digital signal system will be explained with reference to FIG. 1.
First, in recording mode, the HSW generator 516 generates a clock of 30/1.001 Hz (HSW pulses) synchronous with the vertical sync signal of the video signal. The input digital audio signal is applied through the input terminal 501 to the time-axis conversion circuit 502. The time-axis conversion circuit 502 produces the digital audio signal divided into a plurality of sections numbering [Fs/Fv]+A or [Fs/Fv]-B for each head-switching period (vertical sync period of video signal) with reference to the HSW pulse. The digital audio signal produced is controlled to have an average of Fs/Fv pulses in number for each head-switching period. When Fs=48 kHz, Fv=60/1.001 Hz, A=10 and B=8, for example, the digital audio signal is controlled to have 810 or 792 pulses for a head-switching period. In a head-switching period when 792 digital audio signal pulses are produced, 18 dummy data sample pulses are produced at the same time to match the 810 pulses of the head-switching period with the output rate. At the time of producing 810 or 792 digital audio sample pulses in a head-switching period, a discrimination signal is produced for discriminating the number of digital audio signals produced during the head-switching period. The encoding circuit 503 receives an output of the time-axis conversion circuit 502 and adds thereto a predetermined data interleave and an error-correcting redundant data. The format control circuit 504 is supplied with an output data from the encoding circuit 503 and adds thereto a header word including a sync signal, an ID code, a block address, etc. for each predetermined data block. This circuit 504 is also supplied with the discrimination signal and adds it to the header word. The modulation circuit 505 is supplied with an output from the format control circuit 504 and after subjecting it to a predetermined data modulation, records in the magnetic tape through the recording amplifier 506 and the magnetic head 507.
In reproduction mode, on the other hand, the reproduction output of the format control circuit 504 produced through the magnetic head 507, the reproduction amplifier 508 and the demodulation circuit 509 is applied to the reverse format control circuit 510. The reverse format control circuit 510 detects the header word and generates a timing signal for the predetermined data block. Also, the circuit 510 reproduces the discrimination signal for discriminating the number of the digital audio sample pulses produced during the head-switching period by detecting the discrimination signal in the header word. The decoding circuit 511 effects the de-interleave process reverse to the interleave process effected in the encoding circuit 503, or an error-correcting decoding process, and produces 810 or 792 digital audio sample pulses for each head-switching period. The reverse time axis-conversion circuit 512 is supplied with the discrimination signal and the output of the decoding circuit 511 produced in the form of digital audio sample pulses in the number of 810 or 792 for each head-switching period, and produces a digital audio signal of 48 kHz in sampling frequency.
In this conventional method, digital audio sample pulses in the number of 810 or 792 are produced in the number of 800.8 on the average for each head-switching period and stored in memory to be read by a clock of Fs =48 kHz in reproduction mode. No method of generating the timing clock of Fs=48 kHz required for this prior art process has been proposed to date.